1. Field of the Invention
The present invention relates to a Viterbi decoder having a very-low-power-consumption Viterbi decoding LSI and, more particularly, to a portable telephone Viterbi decoder using a CDMA system for performing Viterbi decoding even during a standly mode.
2. Description of the Prior Art
Viterbi decoders for convolution codes have conventionally been used for satellite communication and the like as an error correction system having a very high random error correction capability. This system requires a very high operation speed and a large frame length. A Viterbi decoding LSI must perform memory truncation of truncating path memories at an appropriate state. FIG. 1 shows an example of path memories and a maximum likelihood decision circuit in a Viterbi decoding LSI which satisfies the requirement. As shown in FIG. 1, after the switches are switched between the upper and lower contacts by a path select signal Ai+1( ), the contents of shift registers are shifted between rows and sequentially repeatedly updated at a time. The maximum likelihood decision circuit detects a path having maximum path metric at time i+1. The switch is changed over to a corresponding shift register to read its contents, which serve as a maximum likelihood decoded output. To implement this by one chip, however, many gates must be operated at a high speed, resulting in very high power consumption.
In recent years, Viterbi decoding is being used in a digital portable telephone system and a portable telephone system based on CDMA. These systems use a low operation speed and a relatively small frame length, unlike satellite communication.
In these systems, the power consumption must be low because their power supply is a battery for portability. As a current low-power-consumption Viterbi decoder, one having a dedicated Viterbi decision circuit incorporated in a digital portable telephone system DSP has been reported (see NIKKEI ELECTRONICS, No. 602, 1994, pp. 15-16).
To prolong the telephone conversation time and reduce the battery capacity for enhanced portability, the power consumption must be further reduced. Particularly n the CDMA system for performing Viterbi decoding even during a standly mode, reduction in power consumption is essential.
Of current low-power-consumption Viterbi decoders, one having a dedicated Viterbi decision circuit incorporated in a digital portable telephone system DSP can execute two add-compare-select (ACS) operations within six cycles. However, detection of path memories and maximum likelihood decision necessary for Viterbi decoding are performed by software. In addition, metric information required for ACS operation is frequently externally accessed. Particularly in soft decision, the number of metric information bits increases to increase the overhead. This makes it difficult to reduce the power consumption.
The CDMA system exploits a RAKE receiver. A signal decoded by phase estimation and amplitude estimation at each finger has a squared amplitude for both I and Q signals. In attaining Viterbi decoding robust against level variations such as Rayleigh fading, a metric serving as soft decision information is preferably squared. For this reason, soft decision information has a double bit width. This further increases the overhead in the conventional decoder.
The present invention has been made in consideration of the above situation, and has as its object to provide a small-size, light-weight Viterbi decoder capable of reducing the power consumption and improving the operability.
To achieve the above object, according to the first aspect of the present invention, there is provided a Viterbi decoder for Viterbi-decoding an input signal, comprising a path memory, a shift register having at least 9 constraint length xe2x88x921) bits as the number of stages, and a traceback circuit for inputting, to the shift register, an AND per bit (i.e. bit-wise) between a signal generated by a decoder connected to the shift register and a content of the path memory designated by a traceback address counter.
According to the second aspect of the present invention, there is provided a Viterbi decoder comprising a traceback circuit including a path memory constituted by a first RAM, an ACS circuit including a path metric memory constituted by a second RAM, and a branch metric circuit, wherein the traceback circuit including the path memory has a shift register having at least (constraint length xe2x88x921) bits as the number of stages, a signal generated by a decoder connected to the shift register and a content of the path memory designated by a traceback address counter are ANDed in units of bits, and the AND is input to the shift register.
According to the third aspect of the present invention, there is provided a Viterbi decoder wherein the path memory constituted by the first RAM defined in the second aspect is divided into a plurality of blocks, at least one upper bit of the shift register forms a chip select signal, a divided path memory is selected by the chip select signal, a decoding result of remaining bits of the shift register and a content of the path memory selected by the traceback counter and the chip select signal are ANDed in units of bits, and the AND is input to the shift register.
According to the fourth aspect of the present invention, there is provided a Viterbi decoder wherein the path metric memory constituted by the second RAM defined in the second aspect is divided into a plurality of blocks, each of the divided path metric memories comprises an ACS circuit, and sums corresponding to surviving paths selected by the ACS circuits are written in units of the divided memory groups in storing the sums as maximum likelihood of a state in the path metric memory.
According to the fifth aspect of the present invention, there is provided a Viterbi decoder further comprising an ACS circuit and a traceback circuit which start operating by an ACS start signal and a traceback start signal, the ACS circuit and the traceback circuit being event-driven by the respective start signals.
According to the sixth aspect of the present invention, there is provided a Viterbi decoder wherein when path memory stages in the traceback circuit defined in the second aspect are truncated by an appropriate length corresponding to a plurality of blocks, a truncation range overlaps preceding and succeeding truncation ranges in units of blocks, a traceback start position is set by a maximum likelihood decision circuit, and a start block of one surviving path in a truncation symbol corresponding to a state selected by traceback is used as decoded data.
According to the seventh aspect of the present invention, there is provided a Viterbi decoder wherein the path memory divided into the plurality of blocks defined in the sixth aspect is a ring buffer rotating in units of blocks, traceback starts from last data in a last block, and data corresponding to a start block is used as decoded data.
According to the eighth aspect of the present invention, there is provided a Viterbi decoder wherein a ring buffer formed by the path memory divided into the plurality of blocks defined in the sixth aspect is a RAM, and data update in units of blocks is realized by address control.
According to the ninth aspect of the present invention, there is provided a Viterbi decoder wherein input data corresponding to each of the blocks in the sixth aspect is time-compressed in units of blocks, and ACS processing and traceback are performed at a compression timing.
According to the first aspect, a small-size, light-weight Viterbi decoder capable of reducing the power consumption and improving the operability can be provided.
According to the second aspect, an optimum hardware architecture can be realized with a minimum number of optimized components, compared to a combination of a DSP and a Viterbi accelerator as a conventional architecture. Therefore, a small-size, light-weight Viterbi decoder capable of reducing the power consumption and improving the operability can be provided.
According to the third aspect, a path memory is divided into a plurality of blocks, and each divided path memory is selected by a chip select signal. Accordingly, a lower-power-consumption Viterbi decoder can be provided.
According to the fourth aspect, since a path metric RAM is divided and comprises an ACS circuit for each divided metric, parallel processing can increase the speed. Also, traceback is realized by the above hardware architecture, and a high-speed Viterbi decoder can be provided.
The Viterbi decoder of the present invention defined in the fifth aspect is of the type event-driven by ACS and traceback start signals. The Viterbi decoder can be released from limitations imposed by operation clocks and flexibly designed.
According to the sixth aspect, even if a signal has a long frame, traceback need not be frequently performed because path memories can be truncated in units of blocks. Therefore, a high-power-efficiency Viterbi decoder can be provided.
According to the seventh and eighth aspects, even when the truncation range overlaps preceding and succeeding truncation ranges upon memory truncation, a Viterbi decoder whose memory capacity is decreased by constructing path memories in a ring buffer shape can be provided.
According to the ninth aspect, since input data is time-compressed and processed in units of blocks, an event-driven Viterbi decoder capable of smooth traceback in units of blocks can be provided.